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X86 instructions
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1	1 FROM RING3 TO RING0: EXPLOITING THE XEN X86 INSTRUCTION EMULATOR Andrei Vlad Luțaș Bitdefender Add to Reading List Source URL: labs.bitdefender.com Language: English - Date: 2016-01-22 04:06:36 Computer architecture Computing X86 architecture Interrupts X86 instructions Memory management Interrupt descriptor table Task state segment Global Descriptor Table Interrupt flag X86 Interrupt
2	Microarchitectures Undo Software Security Measures • To implement secure algorithms, software based cryptography utilizes the ISA through instructions or cryptographic extensions. Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:30 Cryptography Advanced Encryption Standard X86 instructions Rambus Side-channel attack AES instruction set Cryptography Research Masking Technology Computing
3	Megaprocessor -Instruction Set James Newman May 2016 Add to Reading List Source URL: megaprocessor.com Language: English - Date: 2016-05-15 10:12:42 Computer architecture Computing Software engineering Instruction set architectures X86 instructions Machine code NOP Nothing DEC Alpha ALGOL 68 R0
4	Chapter 8 Exceptional Control Flow From the time you first apply power to a processor until the time you shut it off, the program counter assumes a sequence of values a0 , a1 , . . . , an−1 Add to Reading List Source URL: csapp.cs.cmu.edu Language: English - Date: 2010-02-14 14:17:30 Computing Computer architecture Software engineering Computer errors Interrupts Control flow X86 instructions Subroutines Unix signal General protection fault Interrupt flag Interrupt
5	Knights Landing (KNL): 2nd Generation Intel® Xeon Phi™ Processor Avinash Sodani KNL Chief Architect Senior Principal Engineer, Intel Corp. Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:27 Computing Computer architecture Computer engineering X86 instructions Intel Corporation Parallel computing Xeon Phi AVX-512 Intel Core CPUID Xeon Haswell
6	Analysts’ Presentation Results FY 2014 May 26, 2015 Minds + Machines Group Limited (MMX) 1 Add to Reading List Source URL: mmx.co Language: English - Date: 2015-11-30 15:05:28 Identifiers Domain name system X86 instructions MMX Computing Top-level domain Domain name
7	Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture Add to Reading List Source URL: www.cs.bu.edu Language: English - Date: 2005-03-23 22:57:42 Computer architecture Computing Computer engineering Central processing unit X86 instructions X86 architecture Parallel computing MMX Streaming SIMD Extensions SIMD Processor register Instruction set
8	You are responsible for the material contained on the following slides, though we may not have enough 9me to get to them in le Add to Reading List Source URL: www-inst.eecs.berkeley.edu Language: English - Date: 2014-02-04 15:27:40 Software engineering Programming language theory Computing Machine code X86 instructions Opcode INT ALGOL 68
9	CS:APP2e Web Aside ASM:SSE: SSE-Based Support for Floating Point∗ Randal E. Bryant David R. O’Hallaron August 5, 2014 Add to Reading List Source URL: csapp.cs.cmu.edu Language: English - Date: 2014-08-05 12:50:10 Computer architecture Computing X86 instructions Computer engineering Streaming SIMD Extensions SSE2 MMX X86 MOVAPD X87 Processor register SSE3
10	Symbolic Crosschecking of Floating-Point and SIMD Code Peter Collingbourne Cristian Cadar Paul H. J. Kelly Add to Reading List Source URL: www.doc.ic.ac.uk Language: English - Date: 2016-03-08 07:04:45 Concurrent computing Computing Computer architecture X86 instructions SIMD AltiVec Streaming SIMD Extensions Processor register SSE2 Symbolic execution MMX Constant folding

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